Simultaneous Multithreading

Program Authorized to Offer Degree Date In presenting this dissertation in partial fulfillment of the requirements for the Doctoral degree at the University of Washington, I agree that the Library shall make its copies freely available for inspection. I further agree that extensive copying of this dissertation is allowable only for scholarly purposes, consistent with " fair use " as prescribed in the U.S. whom the author has granted " the right to reproduce and sell (a) copies of the manuscript in microform and/or (b) printed copies of the manuscript made from microform. " Signature Date 1.1 Utilization of issue slots on (a) a superscalar processor, (b) a superscalar processor with fine-grain multithreading, and (c) a simultaneous multi-3.1 Sources of all unused issue cycles in an 8-issue superscalar processor. : : 23 4.1 Instruction throughput as a function of the number of threads with fine-grain 4.4 Total instruction throughput as a function of the number of threads for each of the six machine 5.2 The pipeline of (a) a conventional superscalar processor and (b) that pipeline modified for an SMT processor, along with some implications of those iii 5.6 Instruction throughput for the 64-entry queue and early I cache tag lookup, when coupled with the RR fetch 5.7 Instruction throughput for the 64-entry queue and early I cache tag lookup, when coupled with the ICOUNT fetch 6.2 The Markov state diagram for a simultaneous multithreading processor. : : 81 6.3 The response times and utilization for both the superscalar CPU and the simultaneous multithreading 6.4 The ratio of the unmodified superscalar's response time to the simultaneous multithreading processor's response time with increasing load on the system. 84 6.5 A queueing model for an interactive system with a single CPU and a single 6.7 The response times for the queueing network with an unmodified super-scalar CPU, and with a simultaneous multithreading 5.2 The result of increased multithreading on some low-level metrics for the base 5.3 Some low-level metrics for the round-robin and instruction-counting priority policies (and the 2.8 fetch partitioning scheme). 5.4 Instruction throughput (instructions per cycle) for the issue priority schemes, and the percentage of useless instructions issued when running with 8 threads. 72 6.1 Completion rates for SMT Markov Acknowledgments I owe thanks to many people who have contributed to this dissertation and other aspects of my academic career. I owe a particular debt to my advisors, Susan Eggers …